Command option
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Represented for
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Options
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-synth
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Synthesis using yosys
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-
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-compile
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Run pack, place, route and generate fasm file
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-
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-src <source path>
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Source file folder
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-
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-d <device>
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Device supported
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ql-eos-s3
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-P <package>
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Packages
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PD64 (BGA), WR42(WLCSP), PU64 (QFN)
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-p <pcf file>
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Fix Placement constraints of IO’s
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-
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-s <sdc file>
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Timing Constraint File (SDC)
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Refer online documents section for SDC constraints supported
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-r <router flag>
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Timing: means no attention is paid to delay. Congestion: means nets on the critical path pay no attention to congestion.
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timing, congestion
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-t <top module>
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Top module of the Verilog design
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-
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-v <Verilog list files>
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Verilog source files
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Only Verilog supported
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-dump <output to be dumped>
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Dump the output format file
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Jlink, post_verilog, header
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