Performing the Post-Layout Simulation (verifying the configuration bits)

Post layout Simulation using the configuration bits, uses the device configuration bit file top_bit.v

The testbench for the counter design is present at:
<Install_Path>/quicklogic-arch-defs/tests/counter_16bit/

The post-layout design netlist is present at:
<Install_Path>/quicklogic-arch-defs/counter_16bit/top_bit.v

The primitive file library file is present at:
<Install_Path>/conda/share/yosys/quicklogic/cells_sim.v

Note

cells_sim.v : This file has the definition for predefined macros

Performing the Post-Layout Timing Simulation

Post layout Timing simulation uses the SDF(Standard Delay Format) file.

The testbench for the counter design is present at:
<Install_Path>/quicklogic-arch-defs/tests/counter_16bit/

The post-layout design netlist is present at:
<Install_Path>/quicklogic-arch-defs/counter_16bit/build/top_post_synthesis.v

The SDF file is present at:
<Install_Path>/quicklogic-arch-defs/counter_16bit/build/top_post_synthesis.sdf

The primitive file library file is present at:
<Install_Path>/quicklogic-arch-defs/share/techmaps/quicklogic/techmap/cells_sim.v

The ram primitive file is present at:
<Install_Path>/quicklogic-arch-defs/share/arch/ql-eos-s3_wlcsp/cells/ram_sim.v

To perform a post-layout simulation:

- Perform a post-layout simulation of the Verilog code use iverilog.
- View the simulation results in the Waveform/ Data Analyzer and verify.

Note

cells_sim.v : This file has the definition for technology mapped macros
ram_sim.v : Has the ram definition