| Command option
|
|
Represented for
|
Options
|
| -synth
|
|
Synthesis using yosys
|
-
|
| -compile
|
|
Run pack, place, route and generate fasm file
|
-
|
| -src <source path>
|
|
Source file folder
|
-
|
| -d <device>
|
|
Device supported
|
ql-eos-s3
|
| -P <package>
|
|
Packages
|
PD64 (BGA), WR42(WLCSP), PU64 (QFN)
|
| -p <pcf file>
|
|
Fix Placement constraints of IO’s
|
-
|
| -s <sdc file>
|
|
Timing Constraint File (SDC)
|
Refer online documents section for SDC constraints supported
|
| -r <router flag>
|
|
Timing: means no attention is paid to delay. Congestion: means nets on the critical path pay no attention to congestion.
|
timing, congestion
|
| -t <top module>
|
|
Top module of the Verilog design
|
-
|
| -v <Verilog list files>
|
|
Verilog source files
|
Only Verilog supported
|
| -dump <output to be dumped>
|
|
Dump the output format file
|
Jlink, post_verilog, header
|